The present invention relates generally to memory devices and, more particularly, to a three dimensional memory cell structure utilizing a plane decoding technique.
Conventional memory architectures employ word lines and bit lines to access the memory cells defined by the memory architecture. Three dimensional memory structures include several memory layers that are stacked upon each other. FIG. 1 illustrates the large area for contact holes required for the independent word lines and bit lines for a three dimensional memory structure. Peripheral circuits 104 are connected to the word lines and bit lines from layers 100a-100n through corresponding contact holes 102a-102n. For example, lines 100a-100n may represent bit lines from the first, second, third and nth layer of the memory structure, respectively. Since lines 100a-100n of the different layers are independent, then respective contact holes 102a-102n cannot be common. It should be appreciated that the same would be applicable if lines 100a-100n were word lines. Thus, the multitude of contact holes requires a large area and leads to reduced array efficiency. As the number of layers increase, the contact area must expand outwards, thereby offsetting density gains achieved through the three dimensional structure.
In general the number of contact holes may be represented by Nx*Nz+Ny*Nz where Nz represents the number of layers, and Nx and Ny are the number of arrays in x- and y-direction, respectively. Where the structure has shared word lines and bit lines the number of contact holes may be represented by 2*Nx+Ny*Nz. Thus, as the number of layers (Nz) increases the number of required contact holes increases dramatically, thereby wasting chip area.
In light of the foregoing, there is a need for a structure and decoding method that limits the number of contact holes for a three dimensional memory structure.